Liquid crystal display device and method of manufacturing the same

ABSTRACT

There are contained a peripheral circuit portion B having first metal patterns formed on a first substrate, a first insulating film formed on the first metal patterns, a second metal pattern formed on the first insulating film, a second insulating film formed on the second metal pattern to have at least a first resin film, and third metal patterns formed on the second insulating film, and a display portion A having an active element formed on the first substrate and covered with the second insulating film and a second resin film, and a pixel electrode formed in a pixel region on the second insulating film and connected electrically to the active element via a hole that is formed in the second insulating film. Accordingly, the liquid crystal display device that has the display portion A and the peripheral circuit portion B is capable of reducing the capacitance between wirings and improving the throughput.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims priority of JapanesePatent Application No. 2001-294582, filed in Sep. 26, 2001, the contentsbeing incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a liquid crystal display deviceand a method of manufacturing the same and, more particularly, a liquidcrystal display device in which a peripheral circuit or a signalprocessing circuit having CMOS field effect transistors is built and amethod of manufacturing the same.

[0004] 2. Description of the Prior Art

[0005] In the active-matrix type liquid crystal display device in whichthe peripheral circuit or the signal processing circuit is built, thethin film transistors (TFTs) are employed as the CMOS transistors of theanalog switch or the inverter in not only the display region but alsothe peripheral circuit or the signal processing circuit.

[0006] The low-temperature polysilicon technology is applied to the thinfilm transistors in the peripheral circuit or the signal processingcircuit like the display region.

[0007] The low-temperature crystallization technology is indispensableto the manufacture of the high performance/low cost peripheral drivercircuit TFTs. The typical crystallization technology that is currentlyput to practical use is the low-temperature crystallization technologyemploying the excimer laser. This excimer laser makes it possible toform the silicon crystal thin film with good quality on the low-meltingglass.

[0008] The basic crystallization method by the excimer laser is given asfollows, for example.

[0009] First, the amorphous silicon (a-Si) starting thin film is formedon the glass substrate by using the thin film forming method such asPECVD (Plasma-Enhanced CVD), etc. Then, in order to improve the laserresistance of the starting thin film, the hydrogen in the a-Si startingthin film is removed by the heating process at 400 to 450° C. Then, thepolysilicon thin film is formed by irradiating the laser beam of theexcimer laser onto the a-Si starting thin film to crystallize it. Then,the crystallinity is improved by processing the polysilicon thin film inthe atmosphere such as hydrogen, steam, etc.

[0010] By employing such polysilicon thin film, the switching TFT arrayis formed in the pixel display portion and also the semiconductorintegrated circuit is formed in the peripheral circuit portion on thesame substrate. Normally the liquid crystal display device in which theperipheral circuits are built is composed of the pixel display portionTFT array, the gate driver circuit, and the data driver circuit. In thedata driver circuit, normally the high performance TFTs that have theoperating frequency in the range of several megahertz (MHz) to severaltens MHz, the field effect mobility of 50 to 300 cm²/Vs, and the properthreshold voltage Vth are used.

[0011] However, the request for the mobility of TFT is not so severe inthe gate driver circuit and the pixel display portion, and the mobilityof more than 20 cm²/Vs, for example, may be employed.

[0012] In contrast, as the new technical trend of the liquid crystaldisplay device, it is intended to attain the ultra high-definitiondisplay panel and the high performance built-in type large-scalesemiconductor circuit.

[0013] First, the ultra high-definition display panel will be explainedhereunder.

[0014] With the progress of the multimedia technology and the mobiletechnology and also the spread of the Internet, it is usually needed toperuse/process a great deal of information. Therefore, the request ofthe ultra high-definition display function in specification for theliquid crystal display device as the man-machine interface is increased.For instance, the large-size high-definition display device of more than200 dpi or the small-size mobile ultra high-definition liquid crystaldisplay device are required in the application fields such as themulti-screen display, the multitasking process, the CAD design, etc.

[0015] Then, the high performance liquid crystal panel built-inlarge-scale semiconductor circuit will be explained hereunder.

[0016] In the low-temperature polysilicon integrated panel, thereappears the technical trend that can accomplish the intelligent panel orthe sheet computer by providing the high performance large-scalesemiconductor integrated circuit to the peripheral circuit portion. Forexample, it is possible that the digital driver, the data processingcircuit, the memory array, the interface circuit, and the CPU are builtin the liquid crystal display panel on the data side.

[0017] The ordinary thin film transistors are employed as the activeelements employed in such peripheral circuit. As set forth in PatentApplication Publication (KOKAI) 2000-36599, for example, respective thinfilm transistors in the peripheral circuit portion and the pixel portionare formed by the same steps, and also the wirings formed on these thinfilm transistors are formed by the same steps.

[0018] For instance, as shown in FIG. 1, the thin film transistor 101 inthe display portion A and the thin film transistor 102 in the peripheralcircuit portion B are formed simultaneously on one substrate 103, andthen these thin film transistors 101, 102 are covered with the firstinterlayer insulating film 104. The polysilicon film 100 constitutingthe thin film transistors 101, 102 is formed by patterning the abovelow-temperature polysilicon film. The gate insulating film 110 is formedbetween the polysilicon film 100 and the gate electrodes 101 g, 102 g.In this case, the gate electrodes 101 g, 102 g are formed at the sametime as the first-layer wiring (not shown).

[0019] Then, the second-layer wiring 105, the second interlayerinsulating film 106, the third-layer wiring 107, and the thirdinterlayer insulating film 108 are formed in sequence on the firstinterlayer insulating film 104. The second-layer wiring 105 is connectedto the thin film transistor 101 in the display portion A and the thinfilm transistor 102 in the peripheral circuit portion B via the holesformed in the first interlayer insulating film 104 respectively. Thethird-layer wiring 107 is connected to the thin film transistor 102 inthe peripheral circuit portion B via the hole formed in the secondinterlayer insulating film 106. The metal constituting the second-layerwiring 105 is used as the black matrix BM in the display portion A.Also, the pixel electrode 109 is formed on the third interlayerinsulating film 108 in the display portion A, and the pixel electrode109 is connected to the source region of the thin film transistor 101.

[0020] In this case, in the liquid crystal display panel, the pixelpitch is reduced smaller with the progress of the high definitiondisplay, and thus the peripheral circuit density is extremely increased.For such purpose, the ultra-high definition panel having the digitaldriver therein and having more than 200 dpi must be formed.

[0021] For example, in the case of the 8.4 type UXGA panel, the pixelnumber is 1600 (horizontal direction)×3×1200 (vertical direction), thedisplay definition is 238 dpi, and the sub pixel pitch is 35.5 μm. Asother example, in the case of the 15 type QXGA panel, the pixel numberis 2048 (horizontal direction)×3×1536 (vertical direction), the displaydefinition is 171 dpi, and the sub pixel pitch is 49.5 μm.

[0022] In order to drive such pixel column of one vertical line, theperipheral circuit consisting of several hundreds to several thousandsTFTs must be installed into such narrow pixel pitch region. Also, inorder to manufacture the high performance low-temperature polysilicon,the intelligent panel, the sheet computer, etc., the large-scaleintegrated circuits such as the digital driver, the data processingcircuit, the memory array, the interface circuit, the CPU, etc. must bebuilt in the peripheral region. Thus, these large-scale integratedcircuits must be installed in the narrow frame region.

[0023] In contrast, because of the requests for the lightweight and thecompactness, the frame allowed for the liquid crystal panel is in therange of several mm from the edge of the glass substrate. Thus, it isimpossible to expect the panel that has the frame of more than 10 mm.

[0024] In case the TFTs are arranged to satisfy the above conditions,the wiring pitch is narrowed. Therefore, there is caused such a newproblem that the floating capacitance between the wirings is increased.

[0025] Also, in the multi-layered wiring structure shown in FIG. 1, theinsulating film must be formed between the uppermost wiring and thepixel electrode respectively, and also the hole for connecting theuppermost wiring and the pixel electrode must be formed in theinsulating film. Therefore, the pixel electrode connecting hole must beformed singularly, and thus there is the possibility that the throughputis lowered.

SUMMARY OF THE INVENTION

[0026] It is an object of the present invention to provide a liquidcrystal display device capable of reducing a capacitance between thewirings and also improving the throughput, and a method of manufacturingthe same.

[0027] According to the liquid crystal display device of the presentinvention, the resin film is formed between the first metal pattern andthe second metal pattern that are formed vertically. Therefore, thefloating capacitance of the multi-layered wiring structure consisting ofthe first metal pattern and the second metal pattern can be reduced andthus the operation frequency of the peripheral circuit portion can beimproved widely. In addition, since the floating capacitance should beseldom considered, the margin of circuit design can be enhanced.

[0028] Also, according to the present invention, the uppermost wiringand the pixel electrode are formed by the same insulating film.Therefore, the pixel-electrode connecting holes in the display portioncan be formed simultaneously with the wiring connecting holes in theperipheral circuit portion, and thus the throughput can be improved.

[0029] In addition, the uppermost metal pattern of the multi-layeredwiring structure in the peripheral circuit portion and the pixelelectrodes in the display portion are covered with the same resin film,e.g., the alignment film. Therefore, the film thickness can be formedeasily thick in contrast to the case where the inorganic insulating filmis formed singly on the uppermost metal pattern, and thus themanufacturing process can be simplified.

[0030] In this case, the above insulating film is also referred to asthe interlayer insulating film. Also, the substrate may be formed of theTFT substrate, and the wiring may be formed of the metal wiring.

[0031] According to the present invention, the transparent conductivefilm constituting the pixel electrodes is formed on the wirings in theperipheral circuit portion. Therefore, the wirings can be protected fromthe external environment before the resin film is formed on the wiringsand the pixel electrodes.

[0032] According to the present invention, the fixed-potential metalpattern (electromagnetic shielding film) is formed of the uppermostmetal layer and also the transmission circuit consisting of themulti-layered metal layer is formed thereunder. Therefore, theelectromagnetic radiation generated when the high frequency signal istransmitted to the transmission circuit can be reduced.

[0033] According to the liquid crystal display device manufacturingmethod of the present invention, the transparent conductive film and themetal layer are formed in sequence on the insulating film in the displayportion and the peripheral circuit portion, then photoresist is coatedon the metal layer, then this photoresist is exposed to form a wiringlatent image in the peripheral circuit portion and form a pixelelectrode latent image in the display portion, and then the resistexposure step of irradiating the exposure light to at least the pixelelectrode latent image at a low exposure amount is applied.

[0034] According to this, if the wiring latent image and the pixelelectrode latent image are changed into visible images as patterns bydeveloping the resist, the thickness of the wiring resist pattern isthinner than that of the pixel electrode resist pattern. Therefore,after the wiring patterns and the pixel electrodes are formed by etchingthe metal layer and the transparent conductive film while using theseresist patterns as a mask, the pixel electrode resist pattern can beremoved while thinning the wiring resist pattern by the oxygen plasma,etc., whereby the metal layer on the pixel electrodes can be selectivelyremoved. That is, the wiring pattern and the transparent pixel electrodecan be formed simultaneously by one resist pattern forming step.

[0035] Also, according to the present invention, if the uppermost wiringand the pixel electrodes are formed together on the same insulating filmin the peripheral circuit portion and the display portion, the metallayer is formed on areas except the display region by using the sputtermask and also the transparent conductive film is formed on theinsulating film in the display region and on or under the metal layer inperipheral circuit portion by the sputter method.

[0036] Therefore, according to one photolithography step, the pixelelectrode consisting of the transparent conductive film can be formed inthe display portion and also the wirings having the double-layeredstructure consisting of the transparent conductive film and the metallayer can be formed in the peripheral circuit portion.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037]FIG. 1 is a sectional view showing the prior art of the TFTsubstrate of the liquid crystal display device;

[0038]FIGS. 2A to 2M are sectional views showing steps of manufacturinga TFT substrate of a liquid crystal display device according to a firstembodiment of the present invention;

[0039]FIG. 3 is a flowchart showing formations of the TFT substrate andan alignment film of the liquid crystal display device according to thefirst embodiment of the present invention;

[0040]FIG. 4 is a plan view showing the TFT substrate according to thefirst embodiment of the present invention;

[0041]FIG. 5 is a partial sectional view showing the liquid crystaldisplay device according to the first embodiment of the presentinvention;

[0042]FIG. 6 is block circuit diagram showing the TFT substrateaccording to the first embodiment of the present invention;

[0043]FIGS. 7A and 7B are sectional views showing steps of manufacturinga TFT substrate of a liquid crystal display device according to a secondembodiment of the present invention;

[0044]FIG. 8 is a partial sectional view showing the liquid crystaldisplay device according to the second embodiment of the presentinvention;

[0045]FIGS. 9A to 9C and FIG. 10 are block diagrams showing a datadriver in a peripheral circuit portion of a liquid crystal displaydevice according to a third embodiment of the present invention;

[0046]FIG. 11 is a circuit diagram showing four bits of a latch circuitof the data driver according to the third embodiment of the presentinvention;

[0047]FIG. 12 is a circuit layout showing two bits of the latch circuitof the data driver according to the third embodiment of the presentinvention;

[0048]FIGS. 13A to 13K are sectional views showing steps ofmanufacturing a TFT substrate of a liquid crystal display deviceaccording to a fourth embodiment of the present invention;

[0049]FIGS. 14A and 14B are views showing steps of a first maskselection sputter method employed in a fifth embodiment of the presentinvention;

[0050]FIGS. 15A and 15B are views showing steps of a second maskselection sputter method employed in the fifth embodiment of the presentinvention;

[0051]FIGS. 16A to 16H are sectional views showing steps ofmanufacturing a TFT substrate of a liquid crystal display deviceaccording to the fifth embodiment of the present invention;

[0052]FIG. 17 is a plan view showing a third-layer metal layer employedin the fifth embodiment of the present invention;

[0053]FIG. 18 is a plan view showing a high frequency signaltransmission circuit of a liquid crystal display device according to asixth embodiment of the present invention;

[0054]FIG. 19 is a sectional view showing the high frequency signaltransmission circuit of the liquid crystal display device according tothe sixth embodiment of the present invention; and

[0055]FIG. 20A is a plan view showing another high frequency signaltransmission circuit of the liquid crystal display device according tothe sixth embodiment of the present invention, and FIG. 20B is asectional view showing the same.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] Embodiments of the present invention will be explained withreference to the accompanying drawings hereinafter.

[0057] (First Embodiment)

[0058]FIGS. 2A to 2M are sectional views showing steps of forming a thinfilm transistor (TFT) substrate of a liquid crystal display deviceaccording to a first embodiment of the present invention.

[0059] First, as shown in FIG. 2A, a silicon oxide (SiO₂) film is formedas an underlying insulating film 2 on an insulating substrate(substrate) 1 such as glass, quartz, resin film, etc. to have athickness of 150 to 300 nm, preferably 200 nm. The underlying insulatingfilm 2 may be formed as a double-layered structure in which a siliconnitride film of 50 nm thickness and a silicon oxide film of 200 nmthickness are formed sequentially. In this case, a #1737 glass substratemanufactured by Corning Co. Ltd., for example, is employed as theinsulating substrate.

[0060] Then, an amorphous silicon film 3 is formed continuously on theunderlying insulating film 2 to have a thickness of 20 to 100 nm,preferably 40 to 50 nm. These films are formed continuously by the PECVD(Plasma-Enhanced CVD) method, for example. Then, the insulatingsubstrate 1 is put in the nitrogen atmosphere, and then the amorphoussilicon film 3 is annealed at 450° C. for 1 hour, whereby the hydrogenis extracted from the amorphous silicon film 3.

[0061] Then, as shown in FIG. 2B, the amorphous silicon film 3 ischanged into a polysilicon film 3 a by irradiating the excimer laser,which has the wavelength of 308 nm and the energy density of 300 to 400mJ/cm², preferably 320 to 350 mJ/cm², onto the overall surface of theamorphous silicon film 3.

[0062] In this case, the amorphous silicon film 3 is formed of notamorphous-silicon hydride (a-Si:H) but low hydrogen-concentrationamorphous silicon (a-Si), the annealing step to extract the hydrogenfrom the silicon film is not needed. The low hydrogen-concentrationamorphous silicon is the amorphous silicon whose hydrogen containingamount is less than 1%, for example.

[0063] Then, as shown in FIG. 2C, by patterning the polysilicon film 3 aby using the resist (not shown) and the reactive ion etching,island-like polysilicon patterns 3 b, 3 c, 3 d are formed in pluraltransistor forming regions of the display portion A, the peripheralcircuit portion B, and other circuit portions (not shown) respectivelyand also the polysilicon film 3 a is left in short-bar regions (notshown) that connect the transistors.

[0064] Then, as shown in FIG. 2D, an SiO₂ film of 80 to 150 nm thicknessis formed as a gate insulating film 4 on the underlying insulating film2 and the island-like polysilicon patterns 3 b, 3 c, 3 d by the PECVDmethod. As the gate insulating film 4, a double-layered structure thatis obtained by forming continuously the silicon oxide (SiO₂) film, whichhas a film thickness of 100 to 150 nm, preferably 120 nm, and thesilicon nitride (SiN_(x)) film, which has a film thickness of 30 to 100nm, preferably 40 to 50 nm, by virtue of the PECVD method, for example,may be employed.

[0065] In addition, an aluminum alloy (metal), e.g., Al—Nd, Al—Sc, isformed on the gate insulating film 4 by the sputter method to have athickness of 300 to 500 nm, preferably 350 nm. The aluminum alloy is thefirst-layer metal layer (first metal layer).

[0066] Then, the aluminum alloy is patterned by the photolithographymethod using the resist pattern. Thus, as shown in FIG. 2E, gateelectrodes 5 b, 5 c, 5 d passing over the island-like polysiliconpatterns 3 b, 3 c, 3 d and other first-layer wiring pattern are formed.A particular example of the first-layer wiring pattern will be describedlater.

[0067] After this, the gate electrodes 5 b, 5 c, 5 d are etched by thewet etching (isotropic etching) to assure the LDD region widths, andthen the gate electrodes 5 b, 5 c, 5 d are further narrowed by theover-etching, whereby LDD (Lightly Doped Drain) region widths are formedon both sides of the gate electrodes 5 b, 5 c, 5 d. Usually the LDDregion width is controlled in the range of 0.5 to 1.5 μm to assure theTFT reliability. In the first embodiment, the LDD region width ΔL iscontrolled smaller than 0.8 μm by adjusting the side-etching time. Ofcourse, ΔL can be controlled freely in the range of 0.5 to 1.5 μm byadjusting the side-etching time. After the widths of the gate electrodes5 b, 5 c, 5 d are defined, the resist pattern left on the gateelectrodes 5 b, 5 c, 5 d is peeled off.

[0068] Then, as shown in FIG. 2F, source regions and drain regions areformed by doping the impurity into the island-like polysilicon patterns3 b, 3 c, 3 d on both sides of the gate electrodes 5 b, 5 c, 5 d.

[0069] In the doping of the impurity, the phosphorus ion (P⁺) is dopedinto the polysilicon patterns 3 b, 3 c, 3 d on the overall surface ofthe insulating substrate 1 by two-step doping method by virtue of theplasma doping equipment having the ion source in the RF discharge systemor the DC discharge system. As the gas for supplying the phosphorus,phosphine (PH₃) that is diluted into 1 to 5% is employed.

[0070] The doping in the first step and the second step intend to formthe low resistance n⁺-regions in source regions 6 s, 7 s, 8 s and drainregions 6 d, 7 d, 8 d of the polysilicon patterns 3 b, 3 c, 3 d and inthe polysilicon patterns in the short bar regions and also form therelatively high resistance n⁻-regions in the LDD regions.

[0071] As the typical conditions of the first step doping, the ionacceleration voltage is set to 10 keV and the phosphorus dosage is5×10¹⁴ to 5×10¹⁵ ions/cm². As the typical conditions of the second stepdoping, the ion acceleration voltage is set to 70 keV and the phosphorusdosage is 5×10¹² to 5>×10¹⁴ ions/cm². According to such conditions, thedopant is passed through the gate insulating film 4 and introduced intothe polysilicon patterns 3 b, 3 c, 3 d.

[0072] The greatest merit of the two-step doping method is that then⁺-region and the n⁻-region can be formed in a self-alignment fashion byone doping step not to break down the vacuum. The above doping isapplied to the island-like polysilicon patterns 3 b, 3 c in the p-typeTFT 6 forming region and the n-type TFT 7 forming region in theperipheral circuit portion B, the island-like polysilicon pattern 3 d inthe n-type TFT 8 forming region in the display portion A, other TFTsilicon patterns, and the short bar regions. For this reason, theinversion doping for inverting the n⁺-type into the p⁺-type and then⁻-type into the p⁻-type in the source regions and the drain regions ofthe p⁻-type TFT respectively must be executed.

[0073] Therefore, the two-step boron (B⁺) doping is applied to thep-type regions by using the plasma doping equipment having the ionsource in the RF or DC discharge system in the situation that the n-typeTFTs and the n-type short-bar regions are covered with the photoresist(not shown). The B⁺ doping in the first step and the second step in theinversion doping intends to form the low resistance p⁺-regions in thesource regions and the drain regions and the short-bar regionsrespectively and also form the relatively high resistance p⁻-regions inthe LDD regions. As the typical conditions of the first step doping inthe inversion doping, the ion acceleration voltage is set to 10 keV andthe boron dosage is 5×10¹⁴ to 5×10¹⁵ ions/cm². As the typical conditionsof the second step doping, the ion acceleration voltage is set to 60 keVand the boron dosage is 5×10¹² to 1×10¹⁴ ions/cm².

[0074] The photoresist used in the inversion doping is peeled off, andthen the activation of the dopant is carried out by using the excimerlaser method that employs the wavelength of 308 nm and the energydensity of 250 to 300 mJ/cm² or the lamp heating method that employs thehalogen lamp, etc. Thus, the sheet resistance of the source regions andthe drain regions is set to less than 5 k Ω, preferably less than 1 k Ωand also the sheet resistance of the LDD regions is set to 1 ×10⁴ to5×10⁶ Ω/□, preferably 5×10⁴ to 1×10⁵ Ω/□.

[0075] With the above, the formation of the n-type TFT and the p-typeTFT and the silicon short bars is completed. In the first embodiment,the n-type TFT 8 is formed in the display portion A and the n-type andp-type TFTs 6, 7 are formed in the peripheral circuit portion B, butsuch transistors are not limited to them.

[0076] Then, as shown in FIG. 2G, the silicon nitride is formed on thegate insulating film 4 and the gate electrodes 5 b, 5 c, 5 d by thePECVD method to have a thickness of 300 to 600 nm, preferably 400 nm.Thus, this silicon nitride is employed as a first interlayer insulatingfilm 9. Therefore, the TFTs 6, 7, 8 are covered with the firstinterlayer insulating film 9. In this case, the silicon oxide may beformed as the first interlayer insulating film 9 in place of the siliconnitride.

[0077] Then, as shown in FIG. 2H, contact holes 9 a to 9 i are formed onthe source regions 6 s, 7 s, 8 s and the drain regions 6 d, 7 d, 8 d andthe gate electrodes 5 b, 5 c, 5 d of the p-type TFT 6 and the n-typeTFTs 7, 8 by patterning the first interlayer insulating film 9 by virtueof the RIE method and the photolithography method using the resistpatterns. As the etching gas of the first interlayer insulating film 9,CF₄ and SF₆ are employed.

[0078] Then, a multi-layered metal film is formed in all contact holes 9a to 9 i and on the first interlayer insulating film 9 by the sputtermethod. As the multi-layered metal film, for example, there is atriple-layered structure in which a Ti film of 100 nm thickness, an Alfilm of 200 nm thickness, and a Ti film of 100 nm thickness are formedin sequence. This multi-layered metal film is the second-layer metallayer (second metal layer).

[0079] Then, as shown in FIG. 2I, wiring patterns 10 a to 10 i, that areextended from the source regions 6 s, 7 s, 8 s and the drain regions 6d, 7 d, 8 d and the gate electrodes 5 b, 5 c, 5 d via the contact holes9 a to 9 i, are formed by patterning the multi-layered metal film bymeans of the photolithography method. In this photolithography method,the RIE method is employed for the etching and also the chlorine etchinggas is employed as the etching gas for the multi-layered metal film(second-layer metal layer) consisting of Ti/Al/Ti. A wiring pattern 10 gconnected electrically to the drain region 8 d of the TFT 8 and thedrain bus line, a wiring pattern 10 h extended from the gate electrode 5d of the TFT 8, and a wiring pattern 10 i connected to the source region8 s of the TFT 8 and then extended upward are provided on the firstinterlayer insulating film 9 in the display portion A.

[0080] The wiring patterns 10 a to 10 i on the first interlayerinsulating film 9 are the second-layer wiring patterns.

[0081] Then, a silicon nitride film 11 for covering the intermediatewiring patterns is formed on the first interlayer insulating film 9 bythe PECVD method to have a thickness of 50 to 200 nm, preferably 100 nm.In addition, a first resin film 12 such as photosensitive polyimideresin, acrylic resin, etc. is formed on the silicon nitride film 11.Preferably the first resin film 12 should have a film thickness of morethan 1.5 μm to get its planarized surface. The first resin film 12 andthe underlying silicon nitride film 11 constitute a second interlayerinsulating film 13.

[0082] Then, as shown in FIG. 2J, holes 13 a, 13 b, 13 c are formed byexposing/developing the first resin film 12. For example, the hole 13 cis formed on the second-layer wiring pattern 10 i that is electricallyconnected to the source region 8 s of the TFT 8 in the display portionA, and also the holes 13 a, 13 b are formed on the second-layer wiringpatterns 10 a, 10 f that are electrically connected to the drain region6 d, the source region 7 s of the TFTs 6, 7 in the peripheral circuitportion B respectively.

[0083] Then, the silicon nitride film 11 under the first resin film 12is etched through via-holes in the first resin film 12. In this case, inorder to control the etching rate of the silicon nitride film 11 to thefirst resin film 12, a ratio of CF₄, SF₆, and O₂ that are employed asthe etching gas of the silicon nitride film 11 is adjusted.

[0084] Then, a titanium film of 100 to 300 nm thickness is formed on thefirst resin film 12 and in the holes 13 a, 13 b, 13 c as a third-layermetal layer (third metal layer) by the sputter method. Then, as shown inFIG. 2K, the third-layer metal layer is patterned by thephotolithography method using the chorine gas and RIE to formthird-layer wiring patterns 14 a, 14 b, 14 c. In this case, a metalmaterial film such as an Al film, an Al multi-layered wiring film, Alalloy and others may be employed as the third-layer metal layer.

[0085] As a result, in the peripheral circuit portion B, a plurality ofTFTs 6,7 are electrically connected via the metal pattern formed of thefirst-layer metal layer, the second-layer wiring patterns 10 a to 10 i,and the third-layer wiring patterns 14 a, 14 b, 14 c. Also, in thedisplay portion A, the source region 8 s of the TFT 8 is extended ontothe second interlayer insulating film 13 via the second-layer wiringpattern 10 i and the third-layer wiring pattern 14 c.

[0086] Then, a transparent conductive film 15 such as indium oxidematerial, ITO, etc. is formed on the first resin film 12 and thethird-layer wiring patterns 14 a, 14 b, 14 c by the sputter method tohave a thickness of 50 to 100 nm, preferably 70 nm. Then, as shown inFIG. 2L, a pixel electrode 15 c that is extracted from the source region8 s of the TFT 8 in the display portion A to extend over the third-layerwiring pattern 14 c and the pixel forming region is formed by patterningthe transparent conductive film 15 by virtue of the normalphotolithography method employing the wet etching.

[0087] In addition, in the peripheral circuit portion B, the transparentconductive film 15 is left to form a shape along the third-layer wiringpatterns 14 a, 14 b except the case where the third-layer wiringpatterns 14 a, 14 b are formed of Al or Al alloy, whereby thetransparent conductive film 15 covers upper surfaces and side surfacesof the third-layer wiring patterns 14 a, 14 b.

[0088] In case the third-layer wiring patterns 14 a, 14 b, 14 c areformed of Al or Al alloy, electrolytic corrosion is caused when the ITOfilm is formed directly on the third-layer wiring patterns 14 a, 14 b,14 c. Therefore, various measures in step or structure such that anelectrolytic-corrosion preventing conductive film, e.g., a Ti film, isformed on the third-layer wiring patterns 14 a, 14 b, 14 c, or the like.In this case, the ITO film also acts as a protection film for thethird-layer wiring patterns 14 a, 14 b in the peripheral circuit portionB. However, in the peripheral circuit portion B, an operation can becarried out unless the transparent conductive film 15 is left on thethird-layer wiring patterns 14 a, 14 b.

[0089] Then, the films on the substrate is heated at the temperature of200 to 300° C. in the hydrogen (H₂) mixed gas atmosphere or the nitrogen(N₂) atmosphere. Such heating process is effective for the performanceimprovement of the TFTs and the characteristic stabilization of thefirst resin film 12.

[0090] With the above steps, as shown in a of FIG. 3, the TFT substrateforming steps are ended.

[0091] Subsequently to this, as shown in FIG. 2M and FIG. 4, analignment film 16 is printed on the second interlayer insulating film 13in the display portion A and the peripheral circuit portion B, so thatthe pixel electrode 15 c and the third-layer wiring patterns 14 a, 14 bare covered with this alignment film 16. The alignment film 16 consistsof a resin such as polyimide resin.

[0092] In the prior art, the third-layer wiring patterns 14 a, 14 b, 14c are covered with the uppermost protection insulating film, that isseparate from the alignment film, and then the alignment film is formedon the uppermost protection insulating film in the panel step. Incontrast, in the first embodiment, as shown in b of FIG. 3, theformation of the uppermost protection insulating film is omitted and issubstituted for the alignment film 16 that is formed in the panel step.

[0093] Meanwhile, in a plan view of FIG. 4, transfer electrodes 17 thatare arranged near four corners of the insulating substrate 1 are formedto extend the common electrodes, which are formed on the opposingsubstrate side, to the TFT substrate side. The silver paste, thespherical material in which nickel or gold is coated on the ultravioletcured adhesives, etc. may be employed. It should take care that thealignment film 16 for covering the peripheral circuit portion B and thedisplay portion A are not formed on the transfer electrodes 17 and theirperipheral areas.

[0094] In FIG. 4, a seal 18 is formed on a peripheral area of theinsulating substrate 1 like a frame to surround the display portion A,the peripheral circuit portion B, the transfer electrodes 17 and thealignment film 16. Also, in the peripheral circuit portion B of FIG. 4,the uppermost wiring patterns 14 a, 14 b, 14 c may be covered with asealing resin film formed in place of the alignment film. In addition,the seal 18 may be formed on the third-layer metal layer after thethird-layer metal layer is left in the sealing region. The adhesivenessof the seal 18 is never made worse by this formation. No trouble of theelectric insulation is caused since the insulating property of thesealing resin is very good.

[0095] By the way, the liquid crystal is dropped onto the insulatingsubstrate 1 on the TFT side or the opposing substrate in FIG. 4 and thenthe insulating substrate 1 on the TFT side and the opposing substrateare pasted together, so that the liquid crystal display device isformed. A sectional view of the liquid crystal display device takenalong a I-I line in FIG. 4 is shown in FIG. 5.

[0096] In the liquid crystal display device shown in FIG. 5, a TFTsubstrate 19 has the display portion A in which the pixel TFTs 8 and thepixel electrodes 15 c are formed on the insulating substrate 1, and theperipheral circuit portion B in which the inverter and the analog switchhaving the TFTs 6, 7 are provided. Also, an opposing substrate 20 isconstructed by forming a planarization film 21, the black matrix BM, thecolor filter CF, a transparent opposing electrode 22, an alignment film23, etc. on a substrate 24. The seal 18 constituting the cell gaps andthe liquid crystal 25 sealed by the seal 18 are put between the TFTsubstrate 19 and the opposing substrate 20. Further, optical films 26,27 such as a polarization plate, etc. are formed on the outside of theTFT substrate 19 and the outside of the opposing substrate 20respectively.

[0097] In the opposing substrate 20, the planarization film 21 on thecolor filter CF may be omitted. Also, it is desired in the opposingsubstrate 20 that, in order to eliminate the influence of theinclination of the liquid crystal molecules in the display portion A,the alignment film 23 should not be formed on the portions that opposeto the peripheral circuit portion B. In addition, the pixel electrodes15 c are connected to the source region 8 s of the TFT 8 via thesecond-layer wiring pattern 10 i. But one hole (not shown) may be formedin the gate insulating film 4 and the first interlayer insulating film9, and then the transparent conductive film constituting the pixelelectrodes 15 c may be connected directly to the source region 8 s viathis hole.

[0098]FIG. 6 is a block circuit diagram showing the above liquid crystaldisplay device.

[0099] The liquid crystal display device shown in FIG. 6 shows threeportions of the display portion A having a plurality of pixel cells, theperipheral circuit portion B, and the input terminal portion C. Thecircuit shown in FIG. 6 can be applied similarly to other embodiments tobe described later.

[0100] In the display portion A, a plurality of pixel cells 28 eachconsisting of the pixel electrode 15 c and the storage capacitance Cs,which are connected to one of source electrodes of a double-gate TFT 8 aand a double-gate TFT 8 b, are provided such that these pixel cells 28are arranged in rows and columns like a matrix fashion. Also, thedisplay portion A has gate bus (scanning bus) lines 29 a that areconnected to gate electrodes of the TFTs 8 a, 8 b and arrangedhorizontally to select the pixel TFTs, and data bus lines 29 b that areconnected to drain electrodes of the TFTs 8 a and arranged vertically totransmit the data signal to the pixel cells 28, etc.

[0101] For instance, in the display portion A of the UXGA format, thetotal number of the pixel cells is 4800×1200, the total number of thegate bus lines 29 a is 1200, and the total number of the data bus lines29 b is 4800.

[0102] The peripheral circuit portion B is formed on a frame region 1 aaround the display portion A on the insulating substrate 1 made ofglass, and consists of scanning line side circuits 30 a, a data sideperipheral circuit 30 b, an electrostatic prevention/repair/preliminarycharge circuit 30 c, etc.

[0103] The scanning line side circuits 30 a are arranged in the frameregion 1 a on the left and right sides of the display portion, and has acircuit configuration to generate a signal for selecting the gate buslines 29 a. Also, the data side peripheral circuit 30 b is arranged inan upper frame region 1 b of the insulating substrate 1, and has acircuit configuration to convert a digital video signal being input fromthe input terminal portion 31 into an analog tone signal and then feedthe data to the display portion A at a predetermined timing. Theelectrostatic prevention/repair/preliminary charge circuit 30 c isarranged in a lower frame region 1 c of the insulating substrate 1.

[0104] The input terminal portion 31 is composed of input terminalgroups connected to two locations (ports). At this time, 24 or 48digital signal lines are provided to each port, and also various controlsignal terminals for driving the scanning line side circuit 30 a areprovided.

[0105] According to the first embodiment, effects and advantagesdescribed hereunder will be obtained.

[0106] A thickness of the first resin film 12 is more than 1.5 μm and arelative dielectric constant thereof is small such as about 3.0.Therefore, the floating capacitances that exist between the wiringpatterns 14 a, 14 b, 14 c formed of the third-layer metal layer on thefirst resin film 12 and the wiring patterns 5 b to 5 d, 10 a to 10 iformed of the first-layer metal layer and the second-layer metal layercan be reduced, and thus the operating frequency of the peripheralcircuit portion B can be largely improved.

[0107] In contrast, like the prior art, if an inorganic insulating filmsuch as an SiNx or TEOS-SiO₂ film is employed as the second interlayerinsulating film 13, a thick film thickness cannot be obtained by the CVDfilm forming technology. In addition, since the relative dielectricconstant 7 to 9 of SiN_(x) and the relative dielectric constant 3.8 to4.2 of SiO₂ are larger than that of the organic resin film, theparasitic capacitances between the third-layer wiring patterns 14 a, 14b, 14 c and the underlying other wiring patterns 5 b to 5 d, 10 a to 10i are increased, and thus a high-frequency operation of the peripheralcircuit portion B becomes difficult.

[0108] Also, if the operation frequency of the peripheral circuitportion B is increased, it is possible to provide various high-frequencycircuits on the data side. For example, it is possible to construct thehigh performance/multi-function peripheral circuits, in which thedigital driver circuit, the I/O circuits, the data processing circuit,the memory array, the CPU, etc., each can be operated at 40 MHz to 100MHz, are provided, within the frame regions 1 a, 1 b, 1 c of theinsulating substrate 1. As a result, it is possible to construct thesheet computer.

[0109] In addition, in light of the layout design of the peripheralcircuit portion B, the parasitic capacitances between the third-layerwiring patterns 14 a, 14 b, 14 c and the underlying wiring patterns 5 bto 5 d, 10 a to 10 i should seldom be taken in consideration. Therefore,the margin of circuit design is enhanced, and also the TFT integratedcircuit of high density can be fabricated.

[0110] Further, the parasitic capacitances between the third-layerwiring patterns 14 a, 14 b, 14 c and the underlying wiring patterns 5 bto 5 d, 10 a to 10 i should not be considered in the peripheral circuitportion B. Therefore, the third-layer wiring patterns 14 a, 14 b can bearranged close to the underlying wiring patterns 5 b to 5 d, 10 a to 10i in the arrangement in the lateral direction, and thus an occupied areaof the peripheral circuit portion B can be reduced. As a result, thelightweight and compact peripheral-circuit integrated liquid crystaldisplay device having the narrow frame liquid crystal display device canbe fabricated.

[0111] In the first embodiment, the alignment films 16 are formed as thesecond resin film on the third-layer wiring patterns 14 a, 14 b in theperipheral circuit portion B. Therefore, in contrast to the prior art inwhich a single insulating film is formed, the fabrication process can besimplified and also the production cost can be reduced.

[0112] In the first embodiment, the transparent conductive film 15 madeof the metal oxide is formed again on the third-layer wiring patterns 14a, 14 b in the peripheral circuit portion B. Therefore, the third-layerwiring patterns 14 a, 14 b can be protected by the transparentconductive film 15 before the panel step is carried out. In addition,since the third-layer wiring patterns 14 a, 14 b are covered with thealignment film 16, the long-term reliability of the third-layer wiringpatterns can be assured.

[0113] Further, since other insulating film is not present between thethird-layer wiring patterns 14 a, 14 b and the transparent conductivefilm 15 in the peripheral circuit portion B, the production process ofthe TFT substrate can be simplified and thus a cost-down effect can beexpected.

[0114] (Second Embodiment)

[0115] Steps of manufacturing a peripheral-circuit integratedpolysilicon reflection type liquid crystal display device employing thetriple-layered metal wiring and the double-layered metal wiring will beexplained as a second embodiment hereunder.

[0116] First, as shown in FIG. 2A to FIG. 2J, the steps required untilthe TFTs 6 to 8 are formed on the insulating substrate 1, then the firstinterlayer insulating film 9, the second-layer wiring patterns 10 a to10 i, and the second interlayer insulating film 13 are formed thereon,and then the holes 13 a, 13 b, 13 c are formed in the second interlayerinsulating film 13 are similar to those in the first embodiment. Thus,their explanation will be omitted hereunder.

[0117] Then, as shown in FIG. 7A, third-layer wiring patterns 32 a, 32 bthat are electrically connected to the TFTs 6,7 via the holes 13 a, 13 bin the first resin film 12 are formed in the peripheral circuit portionB. Also, a reflection pixel electrode 32 c that is connected to thesource region 8 s of the TFT 8 via the hole 13 c in the first resin film12 is formed in the display portion A.

[0118] The third-layer wiring patterns 32 a, 32 b and the reflectionpixel electrode 32 c are formed by following steps. An upper surface ofthe reflection pixel electrode 32 c serves as a reflection surface.

[0119] First, as the third-layer metal layer serving also as thereflection conductive film, a titanium film of 20 to 100 nm thicknessand an aluminum film of 50 to 300 nm thickness are formed in sequence onthe first resin film 12 and in the holes 13 a, 13 b, 13 c by the sputtermethod. Subsequently to this, by patterning the third-layer metal layerby means of the photolithography method using the chlorine gas and RIE,the pixel electrode 32 c is formed in the display portion A and also thethird-layer wiring patterns 32 a, 32 b are formed in the peripheralcircuit portion B. In this case, a single-layer Al film may be formed asthe third-layer metal layer.

[0120] Then, respective films on the insulating substrate 1 are heatedat the temperature of 200 to 300° C. in the hydrogen (H₂) mixed gasatmosphere or the nitrogen (N₂) atmosphere. Such heating process iseffective for the performance improvement of the TFTs 6, 7, 8 and thecharacteristic stabilization of the first resin film 12.

[0121] Then, as shown in FIG. 7B, the alignment film 16 is printed onthe display portion A and the peripheral circuit portion B as the secondresin film. The forming step of the alignment film 16 is a part of thepanel step, as shown in FIG. 3. That is, in the second embodiment, theformation of the uppermost interlayer insulating film is omitted andthis alignment film is used for the interlayer insulating film.

[0122] In FIGS. 10A and 10B, the same references as those depicted inFIG. 2A to FIG. 2M denote the same elements.

[0123] The planar shapes on the insulating substrate 1 on which the TFTs6, 7, 8 and the multi-layered wiring structure are formed as mentionedabove are similar to those in FIG. 4. More particularly, like the firstembodiment, the transfer electrodes 17 are formed near four corners ofthe insulating substrate 1, and preferably the alignment film 16 forcovering the peripheral circuit portion B and the display portion Ashould not be formed on the transfer electrodes 17 and their peripheralareas. In addition, the seal 18 is formed around the insulatingsubstrate 1 like the frame to surround the display portion A, theperipheral circuit portion B, and the transfer electrodes 17.

[0124] The liquid crystal display device according to the secondembodiment is shown in FIG. 8. In FIG. 11, the third-layer wiringpatterns 32 a, 32 b in the peripheral circuit portion B are covereddirectly with the alignment film (second resin film) 16 without theintervention of the transparent conductive film. Also, the pixelelectrode 32 c having the reflection surface is connected to the sourceregion 8 s of the TFT 8 via the second-layer wiring pattern 14 c. In theopposing substrate 20, the planarization film 21 on the color filter CFmay be omitted. Also, it is desired in the opposing substrate 20 that,in order to eliminate the influence of the inclination of the liquidcrystal molecules in the display portion A, the alignment film shouldnot be formed on the portions that oppose to the peripheral circuitportion B.

[0125] Since other structures of the liquid crystal display device shownin FIG. 11 are similar to those in the first embodiment, theirexplanation will be omitted.

[0126] In this case, since the effects and advantages of the secondembodiment are almost similar to those of the first embodiment, theirexplanation will be omitted.

[0127] (Third Embodiment)

[0128] In a third embodiment, as an example of the peripheral circuitwhich is integrated with the 0.4 type UXGA liquid crystal display panelhaving the display resolution of 238 dpi, a method of constructing a8-bit digital data driver employing the structures and the processes inthe first and second embodiments will be explained hereunder.

[0129]FIGS. 9A to 9C show three-type data drivers a part or all of whichare integrated with the liquid crystal display device employing thelow-temperature polysilicon TFTs. The data driver constitutes the dataside peripheral circuit 30 b in FIG. 6, and has a circuit configurationthat converts the digital video signal input from the input terminalinto the analog tone signal and feeds predetermined timing data to thedisplay portion A. In FIGS. 9A to 9C, 8-bit digital input RGB signalsare input into a digital driver 33 on the TFT substrate 19. The RGBsignals are 24-channels of R0 to R7, G0 to G7, and B0 to B7.

[0130] A first-type data driver shown in FIG. 9A is a perfect built-intype that the digital driver 33, a block control circuit 34, an analogswitch series 35, all being surrounded by a broken line, are built inthe TFT substrate 19 in FIG. 5 or FIG. 11.

[0131] A second-type data driver shown in FIG. 9B is a partial built-intype that the block control circuit 34 and the analog switch series 35,both being surrounded by a broken line, are built in the TFT substrate19 in FIG. 5 or FIG. 11. Then, the digital driver 33 is a device that isformed on a single crystal semiconductor substrate and is packaged onthe TFT substrate 19 via TAB packaging or COG packaging.

[0132] A third-type data driver shown in FIG. 9C is a partial built-intype that only the analog switch series 35 that is surrounded by abroken line is built in. The digital driver 33 having a D/A convertingfunction is formed on the single crystal semiconductor substrate and ispackaged on the TFT substrate 19 via TAB packaging or COG packaging. Theblock control circuit 34 consists of an externally-fitted printed board(PT board) circuit.

[0133] In FIGS. 9A to 9C, references 33A₁, 33A₂ are common signal linesthat are formed on the TFT substrate 19 and are connected to an outputside of the digital driver 33 and an input side of the analog switchseries 35.

[0134] Since the first-type shown in FIG. 9A out of such three-type datadrivers has the high integration scale, a configuration of thefirst-type will be examined hereunder. In this case, the TFTs 6, 7, etc.in the peripheral circuit portion B in the first and second embodimentsare applied as the TFTs constituting the data driver.

[0135]FIG. 10 is a view showing configurations of the digital driver 33,the block control circuit 34, and the analog switch portion 35, allbeing incorporated onto the TFT substrate 19.

[0136] The digital driver 33 having an operation frequency of 40 MHzshown in FIG. 10 comprises circuits of a signal input/data dividingcircuit 33 a, a serial-parallel converting portion 33 b, a latch circuit33 c, a level shifter 33 d, a D/A converter (decoder) 33 e, an analogoutput buffer (OP amplifier) 33 f, a clock control circuit 33 g, etc.

[0137] In the data side peripheral circuit 30 b, in order to lower theoperation frequency of the digital driver 33 and reduce theelectromagnetic interference (EMI), four input ports are provided inparallel and also the one-system digital driver 33 is provided everyinput port. That is, four-system digital drivers 33 are constructed inthe data side peripheral circuit 30 b.

[0138] Next, basic operational principles and configurations ofrespective portions of the digital drivers 33 will be explainedhereunder.

[0139] The serial signal of 8×RGB=24 channel is converted into theparallel signal of 300 lines by the serial-parallel converting portion33 b and then transferred to the latch circuit 33 c. The latch circuit33 c holds temporarily the signal and transmits this signal to the levelshifter 33 d and the D/A converter 33 e at predetermined timings. Thelevel shifter 33 d converts the logic level (3 to 5 V) into the liquidcrystal driving voltage level (10 to 15 V). The D/A converter 33 egenerates 256 tone signals from the reference voltage V0 and convertsthe digital tone code into the voltage corresponding to the tone(selected from 256 tones). The signal decoded by the D/A converter 33 eis output to the panel side from the analog output buffer 33 f at apredetermined timing.

[0140] The 4800 sub-pixel cells that are aligned horizontally aredivided into four blocks in timing. In other words, the four-systemdigital drivers 33 four times output simultaneously the tone signals of300 lines in the horizontal period. The number of loading lines per onceis 1200 (4800/4) and the loading time is about {fraction (1/4)}horizontal period ({fraction (1/4)} H).

[0141] Also, 300 video signal lines No.1-No.300 and 1200×4 sets analogswitches 35 a are formed on the output side of the digital drivers 33.The analog switches 35 a are selected in unit of 1200 sets based on theblock control lines BL1 to BL4 fed from the block control circuitportion 34, and thus the output signals of the digital drivers 33 areloaded into the predetermined display portion A. In this manner, theinput display signals are transferred sequentially to the displayportion A in order of block by the digital drivers 33 and the blockcontrol circuit 34, and then converted into the video, which can beperceived by the human being, according to the T-V characteristic of theliquid crystal.

[0142] Since the operation frequency of the polysilicon digital driveris lower than the operation frequency of the digital driver on thesemiconductor LSI, the input data must be converted into the optimumtransfer rate (frequency) in response to the TFT performance. Becausethe mobility of the low-temperature polysilicon TFTs 6 to 8 is less than150 cm²/Vs, the operational margin of the TFTs becomes wide if the clockfrequency is set lower than 80 MHz.

[0143]FIG. 11 is a four-bit equivalent circuit diagram showing the latchcircuit 33 c. The latch circuit 33 c is a line memory circuit that ispositioned between the serial-parallel converting portion 33 b and thelevel shifter 33 d and saves temporarily the input digital signals D1 ato D4 a. The four-bit input digital signals D1 a to D4 a are stored inthe latch cell circuits LP1 to LP4 in response to the LPG signal.

[0144] One-bit latch cell circuit LP1 (LP2, LP3, LP4) consists of onethin film transistor T₁ (T₂, T₃, T₄) and two inverters I₁₁, I₁₂ (I₂₁,I₂₂, I₃₁, I₃₂, I₄₁, I₄₂). In order to save the 8-bit digital signal, 8identical latch cell circuits are needed per one output. Accordingly,the 300 output signals are output from one-system digital driver 33,8×300=2400 latch cell circuits are needed. In FIG. 11, four-bit latchcell circuits LP1 to LP4 are depicted.

[0145]FIG. 12 is a two-bit layout diagram of the latch circuit 33 c. Thelayout diagram of the transistors T1 to T4 and the latch cell circuitsLP2, LP4 shown in FIG. 11 is given.

[0146] The design rule used in the layout design is 3 to 4 μm. The 8-bitlatch circuit (only 2-bits are depicted in FIG. 12) can be installedinto a 71 μm width of the 2-pitch pixel portion at a pixel pitch of 35.5μm of the 8.4 type UXGA panel having the display definition of 238 dpi.

[0147] In FIG. 12, the insulating substrate 1, the underlying insulatingfilm 2, the gate insulating film 4, and other insulating films shown inthe first and second embodiments are omitted.

[0148] In FIG. 12, references 36 a to 36 j denote the first-layer metalwiring respectively, and the first-layer metal wirings 36 e, 36 g, 36 h,36 i, 36 j formed on the island-like silicon film 3 a are also used asthe gate electrode of the thin film transistor. Also, references 37 a to37 p denote the second-layer metal wirings formed on the firstinterlayer insulating film 9 for covering the first-layer metal wirings36 a to 36 j. For example, there are connection wirings 37 a to 37 h, 37j, 37 k, 37 m, 37 n for connecting the island-like silicon layer 3 a andthe first-layer metal wirings 36 a to 36 j, an LPG wiring 37 p fortransmitting a signal LPG, constant voltage wirings 37 i, 370 forapplying a constant voltage V_(DD) to a part of the inverters I₂₁, I₄₁,I₄₂, a ground potential wiring 371 for setting a part of the invertersI₂₁, I₄₁, I₄₂ to a ground potential GND, etc.

[0149] Then, references 38 a to 38 c denote the third-layer metalwirings that are formed on the second interlayer insulating film 13 tocover the second-layer metal wirings 37 a to 37 p. As the third-layermetal wirings 38 a to 38 c, for example, a wiring 38 a connected to thesecond-layer metal wiring 37 g on the drain region of the thin filmtransistor T₃ of the third latch cell circuit LP3 and extracted to thethird latch cell circuit LP3, an output wiring 38 b connected to thefirst-layer metal wiring 36 h of the second latch cell circuit LP2, andan output wiring 38 c connected to the first-layer metal wiring 36 j ofthe fourth latch cell circuit LP4.

[0150] In FIG. 12, the holes for connecting the first-layer metalwirings 36 a to 36 _(j) and the second-layer metal wirings 37 a to 37 f,37 h, 37 j, 37 k, 37 p and connecting the island-like silicon layer 3 aand the second-layer metal wirings 37 a to 37 o are shown as the firstcontact. Also, the hole formed in the second interlayer insulating film13 to connect the third-layer metal wiring 38 a and the second-layermetal wiring 37 g and the hole formed in the second interlayerinsulating film 13 and the first interlayer insulating film 9 to connectthe third-layer metal wiring 36 b and the first-layer metal wirings 36j, 36 h are set forth as the second contact.

[0151] In this case, the first-layer metal wirings are the first-layerwiring patterns of the peripheral circuit portion B in the first andsecond embodiments, the second-layer metal wirings are the second-layerwiring patterns of the peripheral circuit portion B in the first andsecond embodiments, and the third-layer metal wirings are thethird-layer wiring patterns of the peripheral circuit portion B in thefirst and second embodiments.

[0152] As described above, since the triple-layered metal wirings areemployed, the high definition digital driver of more than 200 dpi, whichis difficult for the double-layered metal wirings in the prior art, canbe built in.

[0153] Also, since a film thickness of the first resin film 12 as theupper portion of the second interlayer insulating film 13 is thick andthe relative dielectric constant thereof is small, the parasiticcapacitances between the third-layer metal wirings 38 a to 38 c and theunderlying other metal wirings 37 a to 37 o, 36 a to 36 j become small.Therefore, the high-speed operation at the high frequency such as 40 MHzcan be achieved.

[0154] In addition, the large scale peripheral circuit can be fabricatedby using the loose design rule such as 3 to 4 μm.

[0155] (Fourth Embodiment)

[0156] In the first embodiment, patternings of the third-layer metallayers and the transparent conductive film are carried out separately.In a fourth embodiment, the simplification to execute these patternssimultaneously will be explained hereunder.

[0157] First, like the steps shown in FIG. 2A to FIG. 2I, the TFTs 6 to8 are formed on the insulating substrate 1, and then the firstinterlayer insulating film 9 and the second-layer wiring patterns 10 ato 10 i are formed. These steps are similar to those in the firstembodiment, and thus their explanation will be omitted. However, in thefourth embodiment, as the second-layer wiring patterns 10 a to 10 i, thedouble-layered structure in which a Ti film of 50 nm thickness and analuminum film of 200 nm thickness are formed sequentially is employed,otherwise the single layer structure or the multi-layered structure madeof molybdenum (Mo), titanium, aluminum alloy, etc. is formed.

[0158] Then, as shown in FIG. 13A, the silicon nitride film 11 forcovering the second-layer wiring patterns 10 a to 10 i is formed on thefirst interlayer insulating film 9 by the PECVD method to have athickness of 50 to 200 nm, preferably 100 nm. In addition, the firstresin film 12 such as photosensitive negative-type polyimide resin,acrylic resin, etc. is formed on the silicon nitride film 11. It ispreferable that the first resin film 12 should have a film thickness ofmore than 3 to 4 μm to achieve the planarization of the surface. Thefirst resin film 12 and the underlying silicon nitride film 11constitute the second interlayer insulating film 13. In this case, aninorganic film formed of SiO2, SiNx, etc. and having a thickness of morethan 1 μm may be formed in place of the first resin film 12.

[0159] Then, as shown in FIG. 13B, the second-stage holes 13 a to 13 care formed on the second-layer wiring patterns 10 a to 10 i byexposing/developing the first resin film 12. That is, the hole 13 c isformed on the second-layer wiring pattern 10 i that is electricallyconnected to the source region 8 s of the TFT 8 in the display portionA. In addition, the silicon nitride film 11 under the first resin film12 is etched through the holes 13 a to 13 c in the first resin film 12.In this case, in order to control the etching rate of the siliconnitride film 11 to the first resin film 12, a ratio of CF₄, SF₆, and O₂that are employed as the etching gas of the silicon nitride film 11 isadjusted.

[0160] Then, as shown in FIG. 13C, an ITO film (transparent conductivefilm) 41 of 70 nm thickness, a titanium film of 50 nm thickness, analuminum film of 200 nm thickness are formed successively on the secondinterlayer insulating film 13 and in the holes 13 a to 13 c by thesputter method. The Ti film and the Al film constitute the third-layermetal layer 42. The Ti film is formed as an intermediate metal blockingfilm to prevent the electrolytic corrosion due to the direct contactbetween the ITO film 41 and the Al film. In this case, a molybdenum filmmay be formed as the intermediate metal blocking film.

[0161] Next, a positive-type photoresist 43 is coated on the third-layermetal layer 42 to have a thickness of 3 μm. Then, as shown in FIG. 13D,the photoresist 43 containing the display portion A and the peripheralcircuit portion B is exposed by a normal exposure light amount. At thetime of the first exposure, a first reticle (exposure mask) 44 havinglight-shielding patterns 44 a like a wiring shape and a light-shieldingpattern 44 b like a pixel shape is used.

[0162] Light-irradiated regions 43 a are formed in the photoresist 43 bysuch first exposure.

[0163] Then, the step is shifted to the second exposing step of thephotoresist 43 without the development of the photoresist 43.

[0164] At the time of the second exposure, as shown in FIG. 13E, asecond reticle (exposure mask) 45 having a transmission pattern fortransmitting the exposure light to at least the pixel region of thedisplay portion A and a light-shielding pattern for shielding theoverall peripheral circuit portion B from the light is used. Also, anexposure light amount at the time of the second exposure is set to{fraction (1/3)} to {fraction (2/3)} of the exposure light amount at thetime of the first exposure. Accordingly, the pixel regions onto whichthe light is not irradiated at the time of the first exposure arehalf-exposed.

[0165] As a result, the photoresist 43 in the pixel regions is thehalf-exposed portion, and the photoresist 43 in other wiring patternportions is not exposed. In addition, the exposure light has alreadybeen irradiated to the photoresist 43 in the portions, in which thethird-layer metal layer 42 and the ITO film are not left, by the normallight amount.

[0166] After this, the photoresist 43 is developed. Thus, as shown inFIG. 13F, the photoresist 43 in the peripheral circuit portion B has thethickness t₁ same as that obtained via the normal single exposure,whereas the thickness t₂ of the photoresist 43 in the pixel region inthe display portion A is reduced to about {fraction (1/3)} to {fraction(2/3)} in contrast to the photoresist 43 in the peripheral circuitportion B.

[0167] Then, the third-layer metal layer 42 and the transparentconductive film 41 are etched sequentially by using the patterns of thephotoresist 43 having such film thickness distribution as a mask. Thus,as shown in FIG. 13G, third-layer wiring patterns 46 a, 46 b consistingof the metal layer 42 and the ITO film 41 are formed in the peripheralcircuit portion B, and a pixel electrode 46 c consisting of the ITO film41 is formed in the display portion A.

[0168] Then, as shown in FIG. 13H, the oxygen ashing is carried outunder the condition that the photoresist 43 on the pixel electrode 46 ccan be eliminated but the photoresist 43 can be left in the peripheralcircuit portion B. As a method of adjusting a film thickness of thephotoresist 43, the end point of the etching is decided by detecting thecarbon (C) in the plasma generated in the ashing and then monitoring itssignal intensity. The care not to cause the excessive over-ashing mustbe taken. If the film thickness of the photoresist 43 left on the pixelelectrode 46 c after the third-layer metal layer 42 is etched is assumedas t, the film thickness of the photoresist 43 in the peripheral circuitportion B is reduced by about t+a. Where a is a thickness that isreduced by the over-ashing.

[0169] In this state, the third-layer wiring patterns 46 a, 46 b in theperipheral circuit portion B are covered with the photoresist 43 and thethird-layer metal layer 42 left in the display portion A is exposed.

[0170] Then, as shown in FIG. 13I, the third-layer metal layer 42 on thepixel electrode 46 c is removed by the etching. In this case, in orderto leave the ITO film 41 constituting the pixel electrode 46 c, a metaletchant having a high selective etching ratio to ITO is used. In theperipheral circuit portion B, since the third-layer metal layer 42constituting the third-layer wiring patterns 46 a, 46 b is protected bythe photoresist 43, and such third-layer metal layer 42 is not etched.

[0171] Then, as shown in FIG. 13J, the photoresist 43 is removed. If thefirst resin film 12 is applied as the upper layer portion of the secondinterlayer insulating film 13, there is the possibility that the firstresin film 12 is thinned. Therefore, the film thickness of the firstresin film 12 must be adjusted such that the first resin film 12 is leftin ashing the photoresist 43. In this case, if the upper portion of thesecond interlayer insulating film 13 is formed of the inorganic film,the second interlayer insulating film 13 is never thinned by the ashing.As the second interlayer insulating film 13, a triple-layered structurein which the resin film is put between the inorganic films may beemployed.

[0172] Then, as shown in FIG. 13K, the alignment film (second resinfilm) 16 for covering the wiring patterns 46 a, 46 b and the pixelelectrode 46 c is formed on the second interlayer insulating film 13.

[0173] As described above, according to the fourth embodiment, the pixelelectrode 46 c and the third-layer wiring patterns 46 a, 46 b in thedisplay portion A can be formed by one photolithography step having thehalf-exposure step. Therefore, the manufacturing steps can be simplifiedand the production cost can be reduced.

[0174] (Fifth Embodiment)

[0175] In a fifth embodiment, simplification of steps by forming theabove third-layer metal layer by means of the mask selection sputtermethod will be explained hereunder. As the mask selection sputtermethod, there are various methods according to the difference in formingorder of the transparent conductive film and the third-layer metallayer.

[0176]FIGS. 14A and 14B shows a first mask selection sputter method forforming the third-layer metal layer after the transparent conductivefilm is formed.

[0177] First, as shown in FIG. 14A, a device structure portion 52containing TFTs, first-layer and second-layer metal layers, theinterlayer insulating film, the first resin film, etc. is formed on aninsulating substrate 51. The uppermost layer of the device structureportion 52 is the first resin film. Then, the ITO film 53 as thetransparent conductive film is formed on the device structure portion 52by the normal sputter method.

[0178] Then, as shown in FIG. 14B, a Ti film of 50 nm thickness and anAl film of 200 nm thickness are formed as a third-layer metal layer 54on the ITO film 53 by the sputter in the situation that the displayportion A of the device structure portion 52 is shielded from thesputter source by a sputter metal mask 55. Accordingly, the films 53, 54having a multi-layered structure of ITO/Ti/Al are formed in theperipheral circuit portion B of the device structure portion 52, andonly the single-layer ITO film 53 is formed in the display portion A.

[0179]FIGS. 15A and 15B show a second mask selection sputter method forforming the transparent conductive film after the third-layer metallayer is formed.

[0180] First, as shown in FIG. 15A, the device structure portion 52 isformed on the insulating substrate 51. Then, the Ti film of 50 nmthickness and the Al film of 200 nm thickness are formed sequentially asthe third-layer metal layer 54 on the first resin film of the devicestructure portion 52 by the sputter via the sputter metal mask 55 in thesituation that the display portion A of the device structure portion 52is shielded from the sputter source by using the sputter metal mask 55.

[0181] Then, as shown in FIG. 15B, the sputter metal mask 55 is removedfrom the area over the insulating substrate 51, and the ITO film isformed as the transparent conductive film 53 on the device structureportion 52 and the third-layer metal layer 54 by the normal sputtermethod. Accordingly, the films 53, 54 having a multi-layered structureof Ti/Al/ITO are formed in the peripheral circuit portion B, and onlythe single-layer transparent conductive film 53 is formed in the displayportion A.

[0182] Then, steps of forming the pixel electrode and the third-layerwiring pattern by using the first mask selection sputter method shown inFIGS. 14A and 14B will be explained hereunder.

[0183] First, like the steps shown in FIG. 2A to FIG. 2H, the TFTs 6, 7,8 are formed on the insulating substrate 1, and then the firstinterlayer insulating film 9 and the second-layer wiring patterns 10 ato 10 i are formed. Since their details are similar to the firstembodiment, their explanation will be omitted. In this case, as the filmof the second-layer wiring patterns 10 a to 10 i, the double-layeredstructure in which a Ti film of 50 nm thickness and an aluminum film of200 nm thickness are formed in sequence or the single-layer ormulti-layered structure such as Mo, Ti, Al alloy is formed.

[0184] Then, as shown in FIG. 16A, the silicon nitride film 11 forcovering the second-layer wiring patterns 10 a to 10 i is formed on thefirst interlayer insulating film 9 by the PECVD method to have athickness of 50 to 200 nm, preferably 100 nm. In addition, the firstresin film 12 such as photosensitive polyimide resin, acrylic resin,etc. is formed on the silicon nitride film 11. It is preferable that thefirst resin film 12 should have a film thickness of more than 3 to 4 μmto planarize its surface. The first resin film 12 and the underlyingsilicon nitride film 11 constitute the second interlayer insulating film13. The inorganic film formed of SiO₂, SiN_(x), etc. and having athickness of more than 1 μm may be formed in place of the first resinfilm 12.

[0185] Then, as shown in FIG. 16B, the holes 13 a to 13 c are formed onthe second-layer wiring patterns 10 a to 10 i by exposing/developing thefirst resin film 12. For example, the hole 13 c is formed on thesecond-layer wiring pattern 10 i that is electrically connected to thesource region 8 s of the TFT 8 in the pixel forming region. Then, thesilicon nitride film 11 under the first resin film 12 is etched throughthe holes 13 a to 13 c in the first resin film 12. In this case, inorder to control the etching rate of the silicon nitride film 11 to thefirst resin film 12, a ratio of CF₄, SF₆, and O₂ employed as the etchinggas is adjusted.

[0186] Then, as shown in FIG. 16C, the ITO film of 70 nm thickness isformed as a transparent conductive film 56 on the first resin film 12and in the holes 13 a to 13 c by the sputter method.

[0187] Then, as shown in FIG. 16D, while shielding the transparentconductive film 56 in the display portion A by the sputter metal mask55, a titanium (Ti) film of 50 nm thickness and an aluminum (Al) film of200 nm thickness are formed successively on the transparent conductivefilm 56 in the peripheral circuit portion B by the sputter method. TheTi film and the Al film constitute a third-layer metal layer 57. Likethe fourth embodiment, the Ti film functions as the intermediate metalblocking film. In this case, molybdenum may be formed as theintermediate metal blocking film.

[0188] The arrangement of the display portion A in which only thetransparent conductive film 56 is formed on the insulating substrate 1and the peripheral circuit portions B in which the third-layer metallayer 57 and the transparent conductive film 56 are formed are shownlike a plan view of FIG. 17. In this case, all areas other than thedisplay portion A may be employed as the area in which the third-layermetal layer 57 is formed.

[0189] Then, the sputter metal mask 55 is removed from the area over theinsulating substrate 1, and then positive-type photoresist 58 of 1.5 μmthickness is coated on the third-layer metal layer 57 and thetransparent conductive film 56. Then, as shown in FIG. 16E, byexposing/developing the photoresist 58, a pixel resist pattern 58 a isformed in the display portion A and wiring resist patterns 58 b areformed in the peripheral circuit portion B.

[0190] Then, while using the pixel resist pattern 58 a and the wiringresist patterns 58 b as a mask, the transparent conductive film 56 isetched in the display portion A and also the third-layer metal layer 57and the transparent conductive film 56 are etched sequentially in theperipheral circuit portion B. Thus, as shown in FIG. 16F, a pixelelectrode 59 a is formed in the display portion A and third-layer wiringpatterns 59 b are formed in the peripheral circuit portion B. The pixelelectrode 59 a is connected to the second-layer wiring pattern 10 i andis electrically connected to the source region 8 s of the TFT 8. Also,the third-layer wiring patterns 59 b in the peripheral circuit portion Bare connected to the second-layer wiring patterns 1 a, 10 f via thetransparent conductive film 56 filled in the holes 13 a, 13 b.

[0191] Then, as shown in FIG. 16G, the pixel resist pattern 58 a and thewiring resist patterns 58 b are removed by the oxygen ashing. Then, asshown in FIG. 16H, the alignment film 16 for covering the third-layerwiring patterns 59 b and the pixel electrode 59 a is formed on thesecond interlayer insulating film 13.

[0192] As described above, according to the fifth embodiment, thethird-layer metal layer 57 is formed only in the peripheral circuitportion B by the mask selection sputter method while the transparentconductive film 56 is formed in the display portion A and the peripheralcircuit portion B. Therefore, the pixel electrode 59 a and thethird-layer wiring patterns 59 b can be formed by patterning thetransparent conductive film 56 and the third-layer metal layer 57 viaone photolithography step. As a result, the manufacturing steps can besimplified and the production cost can be reduced.

[0193] In FIG. 16A to FIG. 17, the same references as those in the firstand second embodiments denote the same elements.

[0194] (Sixth Embodiment)

[0195] In a sixth embodiment, a method of constructing a high frequencysignal transmission circuit from the first-layer to third-layer metallayers described in the first, second, fourth, and fifth embodimentswill be explained hereunder, and also a structure in which thethird-layer metal layer is employed as the electromagnetic shielding forthe high frequency circuit will be explained hereunder.

[0196]FIG. 18 is a plan view showing a high frequency signaltransmission circuit formed by patterning the first-layer to third-layermetal layers described in the first, second, fourth, and fifthembodiments, and FIG. 19 is a sectional view showing an electromagneticshielding structure.

[0197] On the TFT substrate, three-color digital display signals(8-bit×3) of red (R), green (G), and blue (B), which are input into highfrequency input terminals RD0 to RD7, GD0 to GD7, BD0 to BD7 of the highfrequency signal transmission circuit 60, are input in the peripheralcircuits via wirings in the high frequency signal transmission circuit60. Also, on the TFT substrate, the high frequency control signals thatare input into control signal terminals SA, SB, SC, SD of the highfrequency signal transmission circuit 60 are input the peripheralcircuits via wirings in the high frequency signal transmission circuit60.

[0198] Although different according to the display formats, in the caseof XGA (horizontal 1024×vertical 768), the master clock frequency isabout 65 MHz in a single port and is about 33 MHz in a dual port. Sincethe electromagnetic radiation is generated in transmitting such highfrequency signal to exert a bad influence upon the environment and thehuman body, the electromagnetic preventing measure is requested.

[0199] The high frequency signal input into the TFT substrate from theoutside is transmitted to a high frequency circuit portion 70, etc. viathe high frequency signal transmission circuit 60 shown in a plan viewof FIG. 18. FIG. 19 is a sectional view taken along a II-II line in FIG.18. In this case, FIG. 18 shows the arrangement of the wirings, etc.

[0200] As shown in FIG. 19, the high frequency signal transmissioncircuit 60 has a first-layer wiring 71 formed on an insulating film 62formed on an insulating substrate 61, a second-layer wiring 72 formed ona first interlayer insulating film 63 for covering the first-layerwiring 71 and the insulating film 62, and a fixed-potential metalpattern 73 formed on a second interlayer insulating film 64 for coveringthe second-layer wiring 72 and the first interlayer insulating film 63.At least the upper portion of the second interlayer insulating film 64is formed of a resin insulating film.

[0201] The first-layer wiring 71 is formed by patterning the first-layermetal layer constituting the gate electrodes 5 b to 5 d. Also, thesecond-layer wiring 72 is formed by patterning the second-layer metallayer constituting the second-layer wiring patterns 10 a to 10 i in thefirst embodiment, for example. In addition, the fixed potential metalpattern 73 is formed by patterning the third-layer metal layerconstituting the third-layer wiring patterns 14 a to 14 c in the firstembodiment, for example.

[0202] The first-layer wiring 71 is formed in parallel in plural at aninterval in the vertical direction (Y direction) in FIG. 18. Also, thesecond-layer wiring 72 is formed in parallel in plural at an interval inthe lateral direction (X direction) in FIG. 18.

[0203] One first-layer wiring 71 is connected to one second-layer wiring72 via a contact hole 63 a formed in the first interlayer insulatingfilm 63.

[0204] The second-layer wiring 72 is connected to the high frequencyinput terminals RD0 to RD7, GD0 to GD7, BD0 to BD7 and the controlsignal terminals SA, SB, SC, SD. The first-layer wiring 71 is connectedto the high frequency circuit portion 70 formed on the insulatingsubstrate 61. This high frequency circuit portion 70 is constructed bythe TFTS, the first-layer wiring patterns, the second-layer wiringpatterns, etc. in the peripheral circuit portion B shown in the firstembodiment.

[0205] The fixed-potential metal pattern 73 on the second interlayerinsulating film 64 is patterned into a shape having a size to cover thefirst-layer wiring 71, the second-layer wiring 72, and the highfrequency circuit portion 70. Also, the fixed-potential metal pattern 73is connected electrically to a fixed potential such as the groundpotential or the like, and thus shields them from the electromagneticwave generated by the transmission of the high frequency signal.

[0206]FIG. 20A is a plan view showing a variation of the sixthembodiment, and FIG. 20B is a sectional view showing the same.

[0207] In FIGS. 20A and 20B, two high frequency circuits 70 a, 70 b inthe peripheral circuit formed on the TFT substrate are a first terminal74 and a second terminal 75 formed on the first interlayer insulatingfilm 63 respectively. The first terminal 74 and the second terminal 75are formed by patterning the second-layer metal layer as the origin ofthe second-layer wiring 72 respectively.

[0208] A plurality of bridge wirings 73 a are formed by patterning thefixed-potential metal pattern 73 on the second interlayer insulatingfilm 64. One end of the bridge wiring 73 a is connected to the firstterminal 74 via a hole 64 a formed in the second interlayer insulatingfilm 64, and the other end of the bridge wiring 73 a is connected to thesecond terminal 75 via another hole 64 b formed in the second interlayerinsulating film 64. As a result, two high frequency circuits 70 a, 70 bare connected electrically via the first terminal 74, the secondterminal 75, and the bridge wiring 73 a.

[0209] Also, the fixed-potential metal pattern 73 that is patterned intoa size that can cover the first-layer wiring 71, the second-layer wiring72, and the high frequency circuits 70 a, 70 b is connected electricallyto the fixed potential such as the ground potential GND or the like.

[0210] In this case, the third-layer metal layer 73 is formed by thesame third-layer metal layer to expand around the bridge wirings 73 a,but is isolated mutually via a clearance S of 3 to 50 μm.

[0211] In this case, a structure in which elements in the same highfrequency circuit are connected by the wiring patterns, which are formedby patterning the third-layer metal layer, may be employed.

[0212] It is desired that the above third-layer metal layer should beformed of a metal layer containing aluminum to get the lower resistancevalue and the sheet resistance should be designed lower than 10 Ω/□. Inthe sixth embodiment, the metal layer having the double-layeredstructure consisting of titanium of 50 nm thickness and aluminum of 200nm thickness is employed as the third-layer metal layer, and the sheetresistance of the metal layer having the double-layered structure isless than 0.2 Ω/□.

[0213] As described above, since the fixed-potential metal pattern 73that is formed by patterning the third-layer metal layer on the secondinterlayer insulating film is connected to the ground potential, theradiation of the electromagnetic wave by the high frequency transmissionwirings can be suppressed. As a result, the high frequency signaltransmission circuit 60 can transmit the high frequency signal at a highS/N (signal/noise) ratio without fail. In addition, since theelectromagnetic radiation from the TFT substrate can be reduced by thefixed-potential metal pattern 73, the electromagnetic radiation of theoverall information system and therefore the above structure cancontribute the construction of the environment-friendly informationsystem. Further, since the high frequency transmission circuit havingthe above structure can prevent the electric oscillation of the highfrequency circuit, the panel operation stability can be improved.

[0214] In the above embodiments, the interlayer insulating film may beexpressed by the insulating film.

[0215] As described above, according to the liquid crystal displaydevice of the present invention, the resin film is formed between thefirst metal pattern and the second metal pattern that are formedvertically. Therefore, the floating capacitance of the multi-layeredwiring structure consisting of the first metal pattern and the secondmetal pattern can be reduced and thus the operation frequency of theperipheral circuit portion can be improved widely. In addition, sincethe floating capacitance should be seldom considered, the margin ofcircuit design can be enhanced.

[0216] Also, according to the present invention, the uppermost wiringand the pixel electrode are formed by the same insulating film.Therefore, the pixel-electrode connecting holes in the display portioncan be formed simultaneously with the wiring connecting holes in theperipheral circuit portion, and thus the throughput can be improved.

[0217] In addition, the uppermost metal pattern of the multi-layeredwiring structure in the peripheral circuit portion and the pixelelectrodes in the display portion are covered with the same resin film,e.g., the alignment film. Therefore, the film thickness can be formedeasily thick in contrast to the case where the inorganic insulating filmis formed singly on the uppermost metal pattern, and thus themanufacturing process can be simplified.

[0218] According to the present invention, the transparent conductivefilm constituting the pixel electrodes is formed on the wirings in theperipheral circuit portion. Therefore, the wirings can be protected fromthe external environment before the resin film is formed on the wiringsand the pixel electrodes.

[0219] According to the present invention, the fixed-potential metalpattern (electromagnetic shielding film) is formed of the uppermostmetal layer and also the transmission circuit consisting of themulti-layered metal layer is formed thereunder. Therefore, theelectromagnetic radiation generated when the high frequency signal istransmitted to the transmission circuit can be reduced.

[0220] According to the liquid crystal display device manufacturingmethod of the present invention, the transparent conductive film and themetal layer are formed in sequence on the insulating film in the displayportion and the peripheral circuit portion, and then the thinpixel-electrode resist pattern is formed in the display portion at thesame time when the thick wiring resist patterns are formed in theperipheral circuit portion. Therefore, after the wiring patterns and thepixel electrodes are formed by etching the metal layer and thetransparent conductive film while using these resist patterns as a mask,the pixel-electrode resist pattern can be removed while thinning thewiring resist pattern by the oxygen plasma, etc., whereby the metallayer on the pixel electrodes can be selectively removed.

[0221] Also, according to the present invention, if the uppermost wiringand the pixel electrodes are formed together on the same insulating filmin the peripheral circuit portion and the display portion, the metallayer is formed on areas except the display region by using the sputtermask and also the transparent conductive film is formed on theinsulating film in the display region and on or under the metal layer inperipheral circuit portion by the sputter method. Therefore, accordingto one photolithography step, the pixel electrode consisting of thetransparent conductive film can be formed in the display portion andalso the wirings having the double-layered structure consisting of thetransparent conductive film and the metal layer can be formed in theperipheral circuit portion.

What is claimed is:
 1. A liquid crystal display device comprising: afirst substrate on which a display portion, that has a pixel matrix,scanning bus lines and data bus lines, and a peripheral circuit portion,that has gate drivers for driving the scanning bus lines and datadrivers for driving the data bus lines, are formed; a second substrateopposed to the first substrate; and liquid crystals put between thefirst substrate and the second substrate; wherein at least a part of theperipheral circuit portion having first metal patterns formed on thefirst substrate, a first insulating film formed on the first metalpatterns, a second metal pattern formed on the first insulating film, asecond insulating film formed on the second metal pattern to have atleast a first resin film, and third metal patterns formed on the secondinsulating film, and the display portion having an active element formedon the first substrate and covered with the second insulating film, anda pixel electrode formed in a pixel region on the second insulating filmand connected electrically to the active element via a hole that isformed in the second insulating film.
 2. A liquid crystal display deviceaccording to claim 1, further comprising a second resin film formed onthe third metal pattern, and wherein the pixel electrodes are formedbetween the second insulating film and the second resin film.
 3. Aliquid crystal display device according to claim 1, wherein leadingmetal patterns that consists of a same material as the third metalpattern and are connected electrically to the active elements are formedon the second insulating film in the display portion, and the pixelelectrodes are formed of a transparent conductive film that is formed onthe leading metal patterns.
 4. A liquid crystal display device accordingto claim 3, wherein the leading metal patterns are constructed by amulti-layered or single-layer metal film having a material same as or aquality of the material substantially similar to the third metal patternin the peripheral circuit portion.
 5. A liquid crystal display deviceaccording to claim 1, wherein a transparent conductive film is formed onthe third metal pattern in the peripheral circuit portion.
 6. A liquidcrystal display device according to claim 1, wherein the pixel electrodeis formed of a metal pattern formed on the second insulating film tohave a reflection surface.
 7. A liquid crystal display device accordingto claim 6, wherein the metal pattern constituting the pixel electrodeis constructed by a multi-layered or single-layer metal film having amaterial same as or a quality of the material substantially similar tothe third metal pattern in the peripheral circuit portion.
 8. A liquidcrystal display device according to claim 1, wherein the pixel electrodein the display portion is formed of a transparent conductive filmpattern, and the transparent conductive film pattern is formed under thefirst metal pattern and the second metal pattern in the peripheralcircuit portion.
 9. A liquid crystal display device according to claim2, wherein the second resin film is an alignment film formed in thedisplay portion or a resin film having a quality of material same as thealignment film.
 10. A liquid crystal display device according to claim2, wherein an insulating seal is formed on the third metal pattern inthe peripheral circuit portion.
 11. A liquid crystal display deviceaccording to claim 1, wherein at least a part of the peripheral circuitportion has thin film transistors formed on the substrate, and the firstmetal patterns are a gate electrode and electric wirings of the thinfilm transistors, and the second metal pattern is source/drainelectrodes and the electric wirings of the thin film transistors.
 12. Aliquid crystal display device according to claim 1, wherein the datadriver is a digital driver that has a register circuit, a latch circuit,a D/A converter circuit, and an analog buffer circuit and employs thefirst metal pattern, the second metal pattern, and the third metalpattern.
 13. A liquid crystal display device manufacturing methodcomprising the steps of: forming a first wiring over a substrate;forming a first insulating film on the first wiring; forming a secondwiring on the first insulating film; forming a second insulating filmcontaining at least a first resin film on the second wiring and thefirst insulating film; forming a third wiring on the second insulatingfilm in a peripheral circuit portion; and forming pixel electrodes onthe second insulating film in a display portion.
 14. A liquid crystaldisplay device manufacturing method according to claim 13, furthercomprising the step of: forming a second resin film on the third wiringformed in the peripheral circuit portion and the pixel electrodes in thedisplay portion.
 15. A liquid crystal display device manufacturingmethod comprising the steps of: forming a lower wiring in a displayportion and a peripheral circuit portion on a substrate; forming aninsulating film on the lower wiring; forming a transparent conductivefilm on the insulating film; forming a metal layer on the transparentconductive film; coating resist on the metal layer; exposing the resistat a first exposure amount by using a first exposure mask; exposing theresist at a second exposure amount having a light quantity smaller thanthe first exposure amount by using a second exposure mask that transmitsa light to the display portion of the resist and shields the peripheralcircuit portion from the light; developing the resist to form a firstresist pattern in the peripheral circuit portion and form a pixel-likesecond resist pattern, that is thinner than the first resist pattern, inthe display portion; etching the metal layer and the transparentconductive film by using the first resist pattern and the second resistpattern as a mask to form an upper wiring in the peripheral circuitportion and form pixel electrodes in the display portion; thinning thefirst resist pattern and removing the second resist pattern; exposingselectively the transparent conductive film of the pixel electrodes byetching selectively the metal layer on upper portions of the pixelelectrodes by using the first resist pattern as a mask; and exposing themetal layer constituting the upper wiring by removing the first resistpattern.
 16. A liquid crystal display device manufacturing methodaccording to claim 15, wherein the upper wiring is connectedelectrically to the lower wiring via the transparent conductive film.17. A liquid crystal display device manufacturing method comprising thesteps of: forming TFT elements and a first wiring in a display portionand a peripheral circuit portion on a substrate; forming an insulatingfilm containing a resin film on the TFT elements and the first wiring;forming contact holes in the insulating film to expose partially thefirst wiring; forming a transparent conductive film in the contact holesand on the insulating film; forming a metal layer on the transparentconductive film; coating resist on the metal layer; exposing the resistat a first exposure amount by using a first exposure mask; exposing theresist at a second exposure amount having a light quantity smaller thanthe first exposure amount by using a second exposure mask that transmitsa light to the display portion of the resist and shields the peripheralcircuit portion from the light; developing the resist to form a firstresist pattern in the peripheral circuit portion and form a pixel-likesecond resist pattern, that is thinner than the first resist pattern, inthe display portion; etching the metal layer and the transparentconductive film by using the first resist pattern and the second resistpattern as a mask to form an conductive pattern in the peripheralcircuit portion and form pixel electrodes in the display portion;thinning the first resist pattern and removing the second resistpattern; exposing selectively the transparent conductive film of thepixel electrodes by etching selectively the metal layer on upperportions of the pixel electrodes by using the first resist pattern as amask; and exposing the metal layer constituting the conductive patternin the peripheral circuit portion by removing the first resist pattern.18. A liquid crystal display device manufacturing method comprising thesteps of: forming a lower wiring in a display portion and a peripheralcircuit portion on a substrate; forming an insulating film on the lowerwiring; forming a transparent conductive film on the insulating film;forming selectively a metal layer on the transparent conductive film inthe peripheral circuit portion and keeping an exposed state of thetransparent conductive film in the display portion; forming resist onthe transparent conductive film and the metal layer; forming a resistpattern by exposing/developing the resist; and etching the metal layerand the transparent conductive film by using the resist pattern as amask to form an upper wiring consisting of the transparent conductivefilm and the metal layer in the peripheral circuit portion and formpixel electrodes made of the transparent conductive film in the displayportion.
 19. A liquid crystal display device manufacturing methodcomprising the steps of: forming TFT elements and an electric wiring ina display portion and a peripheral circuit portion on a substrate;forming an insulating film containing a resin on the TFT elements andthe electric wiring; forming contact holes in the insulating film toexpose partially the electric wiring; forming a transparent conductivefilm on the insulating film; forming selectively a metal conductivelayer on the transparent conductive film; forming photoresist on thetransparent conductive film and the metal conductive layer; forming aresist pattern by exposing/developing the photoresist; and etchingsequentially the metal conductive layer and the transparent conductivefilm by using the resist pattern as a mask to form a multi-layeredwiring consisting of the transparent conductive film and the metalconductive layer in the peripheral circuit portion and form pixelelectrodes made of the transparent conductive film in the displayportion.
 20. A liquid crystal display device manufacturing methodcomprising the steps of: forming TFT elements and an electric wiring ina display portion and a peripheral circuit portion on a substrate;forming an insulating film containing a resin on the TFT elements andthe electric wiring; forming contact holes in the insulating film toexpose partially the electric wiring; forming a metal conductive layeron the insulating film; forming selectively a transparent conductivefilm on the metal conductive layer; forming photoresist on thetransparent conductive film and the metal conductive layer; forming aresist pattern by exposing/developing the photoresist; and etchingsequentially the transparent conductive film and the metal conductivelayer by using the resist pattern as a mask to form a multi-layeredwiring consisting of the transparent conductive film and the metalconductive layer in the peripheral circuit portion and form pixelelectrodes made of the transparent conductive film in the displayportion.
 21. A liquid crystal display device manufacturing methodcomprising the steps of: forming a lower wiring in a display portion anda peripheral circuit portion on a substrate; forming an insulating filmon the lower wiring; forming selectively a metal layer on the insulatingfilm in the peripheral circuit portion and keeping an exposed state ofthe insulating film in the display portion; forming a transparentconductive film on the insulating film and the metal layer; formingresist on the transparent conductive film; forming a resist pattern byexposing/developing the resist; and etching the metal layer and thetransparent conductive film by using the resist pattern as a mask toform an upper wiring consisting of the metal layer and the transparentconductive film in the peripheral circuit portion and form pixelelectrodes made of the transparent conductive film in the displayportion.
 22. A liquid crystal display device comprising: a circuithaving first metal patterns formed on a substrate, a second metalpattern formed on the first metal patterns via a first insulating film,holes formed in the first insulating film to connect the first metalpattern and the second metal pattern, a second insulating film formed onthe second metal pattern, and third metal patterns formed on the secondinsulating film and set to a fixed potential.
 23. A liquid crystaldisplay device manufacturing method according to claim 22, wherein thecircuit is a high frequency signal transmission circuit portion or aperipheral circuit portion.
 24. A liquid crystal display devicemanufacturing method according to claim 22, wherein the third metalpatterns are an electromagnetic radiation suppressing film.
 25. A liquidcrystal display device manufacturing method according to claim 22,wherein a wiring pattern for an electronic circuit function operation,which is formed of a metal layer having a same structure as the thirdmetal patterns, is formed on the second insulating film.